`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:06:58 04/22/2011 
// Design Name: 
// Module Name:    clkdiv 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module clkDivider(
    input clk,
    output q,
    input reset
    );
	 
parameter  maxcount = 1;
parameter BITS = 32;
//count = 1/2 the # of clock ticks per period you want... 1=1/2
reg [BITS-1:0] count;
reg qreg = 0;

always@(posedge clk) begin
	if(reset)
		count <= 0;
	else begin
		if(count < maxcount) begin
			count <= count +1;
			qreg <= qreg;
			end
		else  begin
			count <= 0;
			qreg <= ~qreg;
		end
	end
end

assign q = qreg;

endmodule
